1. Field of the Invention
This invention relates to the field of semiconductor devices, and more specifically, to a process designed to improve the surface planarity of polysilicon gate layers.
2. Background Information
In order to fabricate high performance metal oxide semiconductor (MOS) transistors, it is crucial to control gate electrode linewidths. Improved control of the gate electrode linewidth allows the formation of smaller channel lengths and increases the performance of MOS transistors. Non-planar polysilicon layer surfaces degrade the ability to control linewidths during lithographic processing for gate patterning. This degradation of control is generally due to variations in photoresist thickness and irregular light reflections off the polysilicon surface.
Polycrystalline silicon (polysilicon) is a preferred gate electrode material for MOS devices because it is easy to deposit and easy to dope. Polysilicon, however, due to its grain structure, forms a relatively rough surface layer. It is this rough surface layer of polysilicon that interferes with lithographic patterning and decreases linewidth control.
FIG. 1a illustrates a cross sectional view of polysilicon layer 130 deposited above thin gate oxide layer 120, isolation regions 110 and 111, and substrate 100. The rough surface of polysilicon layer 130 caused by the grain structure of polysilicon is also illustrated in FIG. 1a. The rough surface of polysilicon layer 130 causes reflection and scattering effects during photolithographic patterning of a photoresist.
FIG. 1b illustrates a cross sectional view of mask 150 and photoresist layer 140 coated on the polysilicon layer 130 of FIG. 1a. It is a well known process in the art to pattern polysilicon gate layers using a patterned photoresist. In order to pattern photoresist layer 140, mask 150 is used to block the light. As shown in FIG. 1b mask 150 only covers a portion of photoresist layer 140. The uncovered regions of photoresist layer 140 are exposed to light. Exposure to light causes the uncovered portions of photoresist layer 140 to become soluble. FIG. 1b illustrates mask 150 and photoresist layer 140 being exposed to light. Because the light rays are being reflected and scattered by the rough surface of polysilicon layer 130, regions of photoresist layer underlying the mask are exposed to light and become soluble. It should be noted and it will be obvious to one with ordinary skill in the art that although a positive photoresist process is described, a negative photoresist process may also be used.
After photoresist layer 140 has been subjected to a developing solution only the insoluble portions of photoresist layer 140 remain, as shown in FIG. 1c. The insoluble portions of photoresist layer are the portions of photoresist layer 140 not exposed to light. Due to the reflection and scattering of the light by polysilicon layer 130, photoresist layer 140 is poorly patterned. The features of photoresist layer 140 have poor edge definition and have varying horizontal dimensions.
The patterned photoresist is then used to pattern the polysilicon layer 130 into a gate electrode. Polysilicon gate layer 130 is patterned using well known etch techniques, such as, reactive ion etch (RIE), to form a polysilicon gate electrode as shown in FIG. 1d. Because the patterned photoresist layer 140 (in FIG. 1c) has wavy edges and varying horizontal dimensions, the gate electrode 130 in FIG. 1d is formed with poor edge definition and varying linewidth. Therefore, the poorly patterned photoresist layer can cause the gate electrode to be formed with varying gate-lengths. FIG. 1e illustrates a top view of the gate electrode 130 in FIG. 1d. 
The variation in gate-length of the gate electrode can cause variations in channel length. Variation of the channel length varies the electrical characteristics of an MOS device and must be carefully controlled.
Presently there are several techniques for improving gate electrode linewidth control in the manufacture of high performance MOS transistors. The first technique is known as amorphous silicon deposition. Amorphous silicon deposition eliminates the surface roughness caused by the grain structure of polysilicon, however, a degradation in the electrical performance of the gate electrode is common in pure amorphous silicon gates. Additionally, amorphous silicon deposition has problems with deposition defects and is also more difficult to fully dope.
A second technique for improving linewidth control is the use of an amorphous silicon/polysilicon composite gate electrode. An amorphous silicon layer is deposited first and then a polysilicon layer is deposited on top of the amorphous silicon layer. However, such a composite layer may still exhibit surface roughness unless an intervening oxide layer is deposited or grown above the amorphous silicon layer. Because the amorphous silicon layer is deposited first, crystal growth will occur in the deposition of the top polysilicon layer. Unless an intervening oxide layer is used there is nothing to constrain the smooth surface of the amorphous silicon layer during the deposition of the polysilicon layer. In other words, recrystallization of the amorphous silicon layer cannot be controlled. Consequently, the amorphous silicon layer may recrystallize with a rough surface. Thus, the amorphous silicon/polysilicon composite gate may exhibit the surface roughness found in a pure polysilicon layer, and the poor electrical performance, deposition defects, and decreased dopant uniformity exhibited in pure amorphous silicon gates.
A third technique for improving linewidth control is the use of anti-reflective layers as part of the lithographic process. The use of anti-reflective layers reduces the effect of the surface roughness caused by the grain structure of polysilicon. An anti-reflective layer is highly absorbing and reduces the reflection and scattering effects caused by the rough surface of the polysilicon layer. Anti-reflective layers, however, require special processing equipment and add additional steps, i.e. depositing and etching the anti-reflective layer. The need for special processing equipment significantly increases the cost of manufacturing the MOS transistors. Also, the additional steps required by the use of anti-reflective layers increases the defect level normally associated with the production of MOS transistors.
Another technique for improving linewidth control is the use of dual layer resists when patterning a polysilicon gate electrode. In a dual layer resist a first planarizing resist layer is deposited and a second resist layer is spun on top of the first resist layer. The first resist layer may contain a die such that it exhibits many of the absorbing qualities of an antireflective coating. The second resist layer is generally a constant thickness to aid in the control of thin film interference effects. However, the use of the dual resist increases the cost of manufacturing the MOS transistors and, much like the antireflective coating, requires additional processing steps. Anytime additional processing steps are added increases the likelihood that the defect level normally associated with the production of MOS transistors will increase.
Thus, what is needed is a method for the formation of a gate electrode that combines the electrical performance of polysilicon with the surface planarity of amorphous silicon thereby improving linewidth control using standard lithographic techniques without increasing the defect level already associated with the manufactured of high performance MOS transistors.
The present invention describes a method for improved linewidth control in the patterning of polysilicon layers, which are used to form gate electrodes, in the manufacture of metal oxide semiconductor (MOS) devices. The preferred embodiment of the present invention forms a composite gate electrode by depositing a layer of polysilicon above a substrate and then depositing a layer of amorphous silicon above the polysilicon layer. The two layers are deposited in a single deposition step without breaking vacuum. An anneal step is performed to recrystallize the amorphous silicon layer. The two layers are then patterned and etched using generally known lithographic and etching techniques to form a composite gate electrode. The formation of a composite polysilicon/amorphous silicon gate in an integrated circuit gives the device the electrical performance and doping qualities of a polysilicon gate and also gives the device the smoothness of an amorphous silicon gate which improves line definition during gate patterning.
Additional features and benefits of the present invention will become apparent from the detailed description, figures, and claims set forth below.